A band-reject nested-PLL phase-noise reduction scheme for clock-cleaners

This paper proposes a clock-conditioner architecture that minimizes the incidence of the input signal phase-noise (PN) in phase-locked-loop (PLL)-based cleaners by modifying the corresponding transfer function from band-pass to band-reject. Although the proposed configuration uses two PLLs, just one cut-off frequency exists eliminating the need for ultra narrow-band loops. Relaxed bandwidth requirements translate to smaller capacitor values in the loop filters which considerably reduce the overall footprint of the architecture. A 100 MHz clock-cleaner is demonstrated using ICs fabricated in a 0.5 μm 2P3M CMOS process. Experimental results show a 20dB PN improvement at 1 kHz offset frequency with only 3.5% of the capacitor area used in a state-of-the-art cascade-type PLL clock-cleaner.