A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid

A wide-tuning low-cost PLL architecture with negligible loop filter area is presented. To overcome the static phase error or reference spur problem of the conventional type-I PLL over broad frequency tuning range, a Δ-Σ DAC based real- time frequency acquisition aid method is employed in the PLL voltage domain. Different from other Δ-Σ based frequency acquisition methods mainly used for the type-II all-digital PLL (ADPLL), the proposed method provides inherent quantization noise reduction by the PLL loop filter. Simulation results verify that significant reference spur reduction as well as Δ-Σ noise reduction can be achieved with the proposed architecture.