A clock gated flip-flop for low power applications in 90 nm CMOS

A new clock gated flip-flop is presented. The circuit is based on a new clock gating approach to reduce the consumption of clock signal´s switching power. It operates with no redundant clock cycles and has reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flop is used to design 10 bits binary counter and 14 bits successive approximation register. These applications have been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and have been simulated using Spectre. Simulations with the inclusion of parasitics have shown the effectiveness of the new approach on power consumption and transistor count.