DET FF topologies: A detailed investigation in the energy-delay-area domain

In this paper, a comparison of representative Dual-Edge-Triggered flip-flop topologies is carried out in a 65-nm CMOS technology. The energy efficiency is analyzed together with other aspects, such as the area-delay tradeoff, leakage and clock-load, which are typically neglected in previous works. The investigation highlights the impact of effects that become dominant in nanometer technologies (e.g., local interconnects, leakage) and allows for identifying the most effective FFs belonging to the DET class, as well as to evaluate the suitability of DET topologies for real applications.