Analysis of switching noise for an output driver circuit in an application

Circuits with increasingly switching speed are being integrated in high-density chips. As a result, almost all designs and system applications face the challenge of power-ground integrity and switching noise. This trend brings into correspondingly several negative factors to the circuit and system, including large voltage fluctuation, RLC resonance, etc. in power or ground network. Until now, barely literature has invested in a practical application system explaining this adverse effect, since the loop circuit causing switching noise is difficult to find out in a larger system. In this paper, the switching noise in a plasma display panel (PDP) driver integrated circuit (IC) application is analyzed and an analytical model taking into account the main parasitic inductance in loop circuit is also developed in Saber, interpreting the resonance effect in the power supply. It is then employed and the noise is suppressed by a proper on-chip decoupling capacitance. The verified result from analytical model is in great agreement with testing, and it is proved that the switching noise in the system is decreased by 18%.