Design of a low-power 10GHz frequency divider using Extended True Single Phase Clock (E-TSPC) logic

Author

Bazzazi, Amin ; Nabavi, Abdolreza

Author_Institution

High Educ. Inst. of Mirdamad, Gorgan, Iran

fYear

2009

fDate

22-24 Dec. 2009

Firstpage

173

Lastpage

176

Abstract

This paper presents the design of a 10 GHz divider using Extended True Single Phase Clock (E-TSPC) logic on a 0.18 ??m CMOS technology with 1.8 V supply voltage. This divider contains D-Flip flop with dynamic structure that is based on the ?2 divider and ?8/9 dual modulus prescaler. By optimizing the transistor size in each divider stage and inserting optimized buffers between the stages, the power and area are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. The power consumption of ?2 divider and ?8/9 dual modulus prescaler are 320 ??w and 850 ??w, respectively. High speed low power and smaller area are properties of this design.

Keywords

CMOS logic circuits; buffer circuits; circuit simulation; clocks; flip-flops; frequency dividers; low-power electronics; power consumption; CMOS technology; D-Flip flop; E-TSPC logic; dual modulus prescaler; extended true single phase clock logic; frequency 10 GHz; frequency divider; optimized buffers; post-layout simulation; power 320 muW; power 850 muW; power consumption; size 0.18 mum; supply voltage; voltage 1.8 V; CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Flip-flops; Frequency conversion; Frequency synthesizers; Logic design; Phase locked loops; Voltage; PLL; dynamic structure; frequency divider; high speed; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Trends in Electronic and Photonic Devices & Systems, 2009. ELECTRO '09. International Conference on

Conference_Location

Varanasi

Print_ISBN

978-1-4244-4846-3

Type

conf

DOI

10.1109/ELECTRO.2009.5441145

Filename

5441145