Technology CAD challenges of modeling multi-gate transistors

As the economics of Moores law drives transistor feature scaling, multiple gate devices such as Tri-gate and FinFET transistors have been adopted to control short channel effects. As the device pitch is scaled, traditional strain engineering methods lose effectiveness and parasitics can increase, forcing technologists to evaluate disruptive solutions. Moreover, many local continuum models can no longer accurately describe device behaviour at these scaled dimensions and more advanced models must be adopted to guide process and device development. The challenges of present and future multi-gate device development and the role of technology computer aided design in addressing those challenges are discussed.