Title :
A 5Gbit/s CMOS Clock and Data Recovery Circuit
Author :
Kok-Siang, Tan ; Sulainian, M.S. ; Soon-Hwei, Tan ; Reaz, Mamun B I ; Mohd-Yasin, F.
Author_Institution :
VLSI Research Group, Multimedia University, 63100 Cyberjaya, Selangor, Malaysia.
Abstract :
This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-μm CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ±1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.
Keywords :
Circuits; Clocks; Detectors; Frequency; Jitter; Nonlinear filters; Phase detection; Phase locked loops; Power dissipation; Voltage-controlled oscillators;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
DOI :
10.1109/EDSSC.2005.1635295
