A CMOS Delay-Locked Loop Based Frequency Multiplier for Wide-range Operation

A CMOS delay-locked loop based frequency multiplier is presented. The proposed frequency multiplier can multiply the frequency of input signal without a jitter accumulation problem. Multiplication factor N/2 (N=integer) of the proposed frequency multiplier can be chosen easily according to the number of delay cell and the cascade stage of the multiplier sub-circuits. The frequency mutiplier is simulated using tsmc 0.18 μm CMOS process parameters. The DLL-based frequency multiplier can be operated from 232-MHz to 1.5-GHz with 1.8V supply. The power consumption in the proposed frequency multiplier is 2.215-mW, The DLL core locked time is 4-μs, at 250-MHz. The cycle to cycle jitter of DLL is 10.41-ps.