Simulation of correlated line-edge roughness in multi-gate devices

In this paper, the impacts of correlated line-edge roughness (LER) are investigated. Experimental statistics indicate that, the LER of the two edges in Si channel (Fin or nanowire) have strong cross-correlation, depending on the fabrication process. An improved simulation method based on Fourier synthesis is used to generate pairs of LER sequences with certain cross-correlation. The results show that, device Vth distribution is strongly dependent on the cross-correlation, and can exhibit non-Gaussian distribution. Dual-peak distribution appears and enlarges the variation of Vth significantly. In addition, a new method to extend 2D LER into 3D LER is proposed for future LER investigation.