• DocumentCode
    1988305
  • Title

    Design of pseudo flip-around sample hold- circuit for 10-bit, 5-Msamples/Sec pipeline ADC

  • Author

    Santosh, M. ; Behera, Kanhu Ch ; Bose, S.C.

  • Author_Institution
    IC Design Group, Central Electron. Eng. Res. Inst., Pilani, India
  • fYear
    2009
  • fDate
    22-24 Dec. 2009
  • Firstpage
    100
  • Lastpage
    103
  • Abstract
    This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC. The sample-hold circuit is simulated in 0.35 ??m Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal input and a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1 mV, SNR of 60 dB. The layout of the sample hold circuit occupies an area of 0.007 mm2 and consumes 1.7 mW of power.
  • Keywords
    analogue-digital conversion; sample and hold circuits; Austria Microsystems technology; pipeline ADC; power 1.7 mW; pseudo flip around sample hold circuit; sampling clock; size 0.35 mum; Circuit simulation; Clocks; Feedback circuits; Operational amplifiers; Output feedback; Pipelines; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; ADC; Flip-around; SNR; Sample-and-Hold;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Emerging Trends in Electronic and Photonic Devices & Systems, 2009. ELECTRO '09. International Conference on
  • Conference_Location
    Varanasi
  • Print_ISBN
    978-1-4244-4846-3
  • Type

    conf

  • DOI
    10.1109/ELECTRO.2009.5441162
  • Filename
    5441162
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1988305