Title :
High speed circuit techniques in a 150 MHz 64 M SDRAM
Author :
Lines, Valerie ; Abou-Seido, Mammoun ; Mar, Cynthia ; Achyuthan, Arun ; Miyamoto, Sampei ; Murashima, Yoshihiro ; Sakuma, Shinzo
Author_Institution :
MOSAID Technol. Inc., Canada
Abstract :
This paper outlines three methods used to decrease the access time in a 64 M SDRAM. The access time from the read command, Taa, is reduced by the use of a novel column redundancy scheme with easy programming and by the use of current sensing in the data output path. The access time from the clock, Tac, is reduced by the use of a digital DLL whose functionality can be tested with on chip test functions
Keywords :
DRAM chips; delay circuits; redundancy; 150 MHz; 64 Mbit; SDRAM; chip test functions; column redundancy scheme; current sensing; digital DLL; high speed circuit techniques; programming; synchronous DRAM; Circuit faults; Clocks; Decoding; Delay; Fuses; Integrated circuit interconnections; Redundancy; SDRAM; Technological innovation; Testing;
Conference_Titel :
Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8099-7
DOI :
10.1109/MTDT.1997.619388
