Double gate underlap FinFET device optimization and application in SRAM design at 15 nm

In this work an attempt has been made to optimize the double gate underlap FinFET devices so as to approach the ITRS targets for the year 2015 for HP (High Performance) applications. Source/Drain doping engineering, gate dielectric engineering, spacer engineering and metal gate work function engineering have been explored for achieving optimal device characteristics. Quantum mechanical effects which are important in the nanometer regime have been accounted for in the device simulations for obtaining a realistic picture. Also, a 6T SRAM cell has been designed using FinFETs with 15 nm gate lengths and its performance has been evaluated with respect to the noise margins based on the conventional butterfly curves as well as N-curves using mixed mode simulations.