Impact of high-k dielectrics and spacer layers on the elctrical performance of symmetrical double gate MOSFETs

In this paper, analytical models for threshold voltage V_t and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting V_t and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate V_t, S and drain induced barrier lowering (DIBL) of DG MOSFETs with different gate dielectrics for various values of effective oxide thickness (EOT). Also the effect of sidewall spacers on V_t has been predicted. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the reported simulated data.