A semi-static threshold-triggered delay element for low power applications

Delay elements are used in integrated circuits (ICs) to meet design specific timing requirements. Delays are often generated by increasing the input transition times. For long delays, such a signal generally results in prolonged short-circuit current either within the delay element itself or at the subsequent stage, elevating the overall power consumption of the system. In this paper, a novel CMOS semi-static threshold triggered delay element architecture is proposed, that can also be configured to work with other conventional delay elements, to minimize the short-circuit current over a wide delay range resulting in a predictable output delay and reduced power consumption. The semi-static threshold-triggered delay element is fabricated in a commercial 0.35 μm CMOS technology and comparative results show significant improvements in operating range and power consumption over other well-known delay elements.