DocumentCode :
1989125
Title :
Integration Design of Chip and Package for Cost-Effective High-Speed Applications
Author :
Chen, Nansen ; Lin, Hongchin ; Chen, Nan-Cheng ; Wu, Roger ; Chou, Tomson ; Chien, Herbie
Author_Institution :
Department of Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan, E-mail: nansen@seed.net.tw
fYear :
2005
fDate :
19-21 Dec. 2005
Firstpage :
621
Lastpage :
624
Abstract :
Low cost is the trend for consumer electronics. However, the challenges of the LCD-TV processor using cost-effective two-layer ball grid array (BGA) packages suffer from serious crosstalk and return loss due to lack of a solid plane to suppress the coupling effect and control the trace impedance. Two types of two-layer BGA packages were measured and simulated using a 3D full-wave electromagnetic field solver and an EM-based 3D parasitic extractor to analyze their speed limitations and power coupling between the signals and the power net. The results indicated the signal coupling is the dominant factor for insertion loss. Thus, the design guidelines and specifications using two-layer BGA packages are proposed for development of the next generation processors.
Keywords :
Analytical models; Consumer electronics; Costs; Crosstalk; Electromagnetic measurements; Electronics packaging; Impedance; Power measurement; Solids; Velocity measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
Type :
conf
DOI :
10.1109/EDSSC.2005.1635350
Filename :
1635350
Link To Document :
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