High Speed Low Power CMOS Comparator Dedicated to 10it, 20MHz Pipeline ADCs for RF Applications

Author

Guermaz, M.B. ; Bouzerara, L. ; Slimane, A. ; Belaroussi, M.T. ; Lehouidj, B. ; Zirmi, R.

Author_Institution

Microelectronics and Nonotechnologies Division, Centre de Développement des Technologies Avancées, cité 20, Août 1956 BP.17, Baba Hassen, 16303, Algiers, Algeria. E-mail: guerrmaz@hotmail.com

fYear

2005

fDate

19-21 Dec. 2005

Firstpage

657

Lastpage

660

Abstract

In this paper, a differential comparator featuring a high speed of conversion, is described and analyzed. The designed comparator is intended to be implemented in a 10bit, 20MHz pipeline Analog-to-Digital Converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The analyses and simulation results which have been obtained using 0.8μm CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 1 7.3ns, a good accuracy and a low power consumption of about 0.8mW. The predicted performance is verified by analysis and simulations using PSPICE tool.

Keywords

Analog-digital conversion; Analytical models; CMOS process; Clocks; Pipelines; Power supplies; Radio frequency; Switched capacitor networks; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2005 IEEE Conference on

Print_ISBN

0-7803-9339-2

Type

conf

DOI

10.1109/EDSSC.2005.1635360

Filename

1635360