Title :
A Self-Biased FET Multiplier
Author :
Cuhaci, M. ; Stubbs, M.G.
Author_Institution :
Communications Research Centre, P.O. Box 11490, Ottawa, Ontario K2H 8S2
Abstract :
A self-biased FET multiplier circuit that utilizes the gate non-linearity to generate harmonics of the input signal is presented. The concept was demonstrated with designs of 4 to 16 GHz and 14 to 56 GHz X4 multipliers. Although the approach does not exhibit conversion gain, it is very attractive for MMIC applications because it uses standard FET technology and requires no external bias.
Keywords :
Attenuation; Circuits; Delay; FETs; Frequency; Gallium arsenide; Insertion loss; Resistors; Signal analysis; Signal generators;
Conference_Titel :
Microwave Conference, 1984. 14th European
Conference_Location :
Liege, Belgium
DOI :
10.1109/EUMA.1984.333409
