Title :
ARM7 compatible 32-bit RISC processor design and verification
Author :
Jeong, Geun-young ; Park, Ju-Sung ; Jo, Hyun-woo ; Yoon, Byung-woo ; Lee, Myung-jin
Author_Institution :
Samsung SDI, South Korea
fDate :
26 June-2 July 2005
Abstract :
The design and verification of a 32-bit general-purpose microprocessor, which is compatible with ARM7 RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were tested. The designed core was emulated to check its proper operation for various applications, such as ADPCM, SOLA (voice speed variation), MP3 decoding. Finally it was implemented in 0.5μm CMOS process and it carried out successfully those algorithms.
Keywords :
CMOS logic circuits; field programmable gate arrays; integrated circuit design; logic design; logic simulation; microprocessor chips; reduced instruction set computing; 0.5 micron; 3-stage pipeline; 32 bit; ADPCM; ALU; ARM7 RISC core; ARM7 compatible processor; CMOS process; MAC; MP3 decoding; RISC processor design; SOLA; general-purpose microprocessor; logic simulation; low complexity; low power; processor architecture; processor verification; register banks; voice speed variation; CMOS logic circuits; CMOS process; Decoding; Digital audio players; Microprocessors; Pipelines; Process design; Reduced instruction set computing; Registers; Testing;
Conference_Titel :
Science and Technology, 2005. KORUS 2005. Proceedings. The 9th Russian-Korean International Symposium on
Print_ISBN :
0-7803-8943-3
DOI :
10.1109/KORUS.2005.1507795
