Title :
Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder
Author :
Liu, Zhen ; Jia, Song ; Chen, Zhongjian ; Zhang, Xing ; Ji, Lijiu
Author_Institution :
Institute of Microelectronics, Peking University, Beijing, P. R. China. E-mail: zliu@ime.pku.edu.cn
Abstract :
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.
Keywords :
Analog-digital conversion; Bandwidth; Binary codes; Circuit simulation; Circuit stability; Circuit synthesis; Embedded system; Interpolation; Power dissipation; Voltage;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
DOI :
10.1109/EDSSC.2005.1635364
