DocumentCode :
1989533
Title :
Sub-50-nm Asymmetric Graded Low Doped Drain (AGLDD) Vertical Channel nMOSFET
Author :
Zhou, F.L. ; Huang, R. ; An, X. ; Guo, A. ; Xu, X.Y. ; Zhang, X. ; Zhang, D.C. ; Wang, Y.Y.
Author_Institution :
Institute of Microelectronics, Peking University, Beijing, 100871, China.
fYear :
2005
fDate :
19-21 Dec. 2005
Firstpage :
679
Lastpage :
682
Abstract :
40-nm and 32-nm channel length vertical nMOSFETs with an asymmetric graded low doped drain (AGLDD) structure (the LDD region only on the drain side) were experimentally demonstrated. Due to remarkably reduced peak electric field near the drain junction compared with conventional LDD structure, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short channel effects dramatically. The fabricated device with 32-nm channel length, 4.0-nm gate oxide thickness still shows excellent short channel performance as the off-state leakage current (Ioff) and the ratio of the on-state driving current (Ion) to Ioffare 3.7 X 10-11μA/μm and 2.1 X 106, respectively.
Keywords :
Asymmetric graded low doped drain (AGLDD); Vertical channel nMOSFET; low doped drain (LDD); short channel effects (SCEs); CMOS process; CMOS technology; Doping; Etching; Leakage current; Lithography; Logic devices; MOSFET circuits; Microelectronics; Power MOSFET; Asymmetric graded low doped drain (AGLDD); Vertical channel nMOSFET; low doped drain (LDD); short channel effects (SCEs);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
Type :
conf
DOI :
10.1109/EDSSC.2005.1635366
Filename :
1635366
Link To Document :
بازگشت