Micro-architecture generation and simulation from high-level synthesis environment

Summary form only given, as follows. Existing techniques in high-level synthesis mostly assume a simple controller architecture model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptance of behavioral synthesis, the application of these methods for the design of programmable controllers is of fundamental importance in embedded system technology. We describe an important extension of an existing architectural synthesis system targeting the generation and simulation of ASIP reprogrammable architectures. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly simulate and evaluate the trade-offs of hardware decisions.