Linear filtering using reconfigurable computing

Author

Diab, H. ; Majzoub, S.

Author_Institution

Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon

fYear

2003

fDate

14-18 July 2003

Firstpage

15

Abstract

Summary form only given. We present the mapping and performance analysis of a linear filtering algorithm on one of the reconfigurable computing (RC) prototypes, MorphoSys (M1) system. Mapping of a linear filtering algorithm, namely convolving a filter kernel across an image, onto this hardware is proposed. A performance analysis study is examined to evaluate the efficiency of the algorithm execution on the M1 RC system. For instance, an algorithm to convolve 8/spl times/8 image pixels with 3/spl times/3 filter kernel on the M1 8/spl times/8 RC array was run. Numerical examples were simulated to validate our results using the MorphoSys mULATE program, which simulates MorphoSys operations. Results showed that MorphoSys yielded a superior performance compared to the TMS320C40 DSP microprocessor.

Keywords

digital simulation; filtering theory; image morphing; parallel processing; performance evaluation; reconfigurable architectures; 2D convolution; DSP microprocessor; M1 system; MorphoSys system; RC array; RC prototype; image pixel convolution; linear filtering algorithm; parallel processing; performance analysis; reconfigurable computing; reconfigurable system; Digital signal processing; Filtering algorithms; Hardware; Kernel; Maximum likelihood detection; Nonlinear filters; Numerical simulation; Performance analysis; Pixel; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Systems and Applications, 2003. Book of Abstracts. ACS/IEEE International Conference on

Conference_Location

Tunis, Tunisia

Print_ISBN

0-7803-7983-7

Type

conf

DOI

10.1109/AICCSA.2003.1227452

Filename

1227452