16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology

Author

Tsai, C.-Y. ; Efland, T. ; Pendharkar, S. ; Mitros, J. ; Tessmer, A. ; Smith, J. ; Erdeljac, J. ; Hutter, L.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

367

Lastpage

370

Abstract

In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL), (2) two n-type dopings in the drift region, and (3) shrink from 1.0 /spl mu/m to 0.72 /spl mu/m. The R/sub sp/ vs. BV/sub dss/ trend for these devices is the best reported to date for conventional lateral technology: @V/sub gs/=12.75 V (3 MV/cm) R/sub sp/=0.95 m/spl Omega/ cm/sup 2/, BV=69.3 V; R/sub sp/=0.68 m/spl Omega/ cm/sup 2/, BV=50.0 V; R/sub sp/=0.45 m/spl Omega/ cm/sup 2/, BV=33.0 V; R/sub sp/=0.36 m/spl Omega/ cm/sup 2/, BV=19.0 V; for 60, 40, 25, and 16 V rated conventional LDMOS devices.

Keywords

BiCMOS analogue integrated circuits; ion implantation; power MOSFET; power integrated circuits; 0.72 mum; 16 to 60 V; 16-60 V rated; BiCMOS power technology; LDMOS; LOCOS extension region; RESURF principles; breakdown voltage; conventional lateral technology; drift region; n-type dopings; optimized off-set photo aligned coimplanted double-diffused well; performance improvements; Application software; Automotive engineering; BiCMOS integrated circuits; Computer peripherals; Doping; Instruments; Intelligent vehicles; Isolation technology; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650401

Filename

650401