Spatial- and temporal-reliability aware design for nano-scale VLSI circuits

This paper analyzes two of the most significant circuit reliability degradation phenomena in current CMOS technology, namely, temporal Negative Bias Temperature Instability (NBTI) for PMOS transistors and spatial Random Dopant Fluctuation (RDF) for both NMOS and PMOS nano-scale transistors. Among many models, Reaction-Diffusion model used for analyzing NBTI and width dependant model proposed for RDF simulations can currently get closest results to real cases. However, in most of the previous work, the causes and effects of NBTI and RDF were investigated individually. In this paper, we try to exploit how they act together to influence threshold voltage (Fth) and, hence, circuit performance. The simulation result shows that if a PMOS transistor suffers from severe RDF effect, NBTI effect inflicts more damage to it in terms of device performance. At the end, some possible methods of weakening the negative effects of NBTI and RDF are proposed and evaluated.