Hot-carrier reliability in submicrometer LDMOS transistors

Author

Versari, R. ; Pieracci, A. ; Manzini, S. ; Contiero, C. ; Ricco, B.

Author_Institution

Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

371

Lastpage

374

Abstract

This paper provides a physical basis for the experimentally determined hot-electron-limited safe operating area of submicrometer LDMOS transistors under static bias conditions. The physical interpretation of the device behavior is based on the analysis of the bias-dependent gate and substrate currents and of the relative induced degradation.

Keywords

hot carriers; power MOSFET; semiconductor device models; semiconductor device reliability; 0.6 mum; 16 V; bias-dependent gate currents; bias-dependent substrate currents; hot-carrier reliability; hot-electron-limited safe operating area; power LDMOS transistors; relative induced degradation; static bias conditions; submicrometer LDMOS transistors; Circuit synthesis; Degradation; Doping profiles; Helium; Hot carriers; Implants; MOSFETs; Microelectronics; Substrates; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650402

Filename

650402

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1990227