Title :
A Low Power, High SFDR, ROM-Less Direct Digital Frequency Synthesizer
Author :
Jafari, H. ; Ayatollahi, A. ; Mirzakuchaki, S.
Abstract :
This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is -91.5ldBc. A DDFS IC has been designed in HP 0.5μm standard N-Well CMOS process technology, and that´s layout has 2.489mm2area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz.
Keywords :
Direct digital frequency synthesizer (DDFS); ROM-Less; frequency synthesizer; CMOS integrated circuits; Dynamic range; Energy consumption; Frequency control; Frequency synthesizers; Function approximation; Genetic algorithms; Polynomials; Read only memory; Taylor series; Direct digital frequency synthesizer (DDFS); ROM-Less; frequency synthesizer;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
DOI :
10.1109/EDSSC.2005.1635406
