Title :
Design for Manufacturability of Sub-100 Nanometer Standard Cells
Author :
Xuemei, Ji ; Peiyong, Zhang ; Zheng, Shi ; Xiaolang, Yan
Author_Institution :
Institute of VLSI Design, Zhejiang University, Hangzhou, China, E-mail:,jixm@vlsi.zju.edu.cn
Abstract :
To solve the issues of that the feature size is approaching the theoretic limit of existing exposure system in modern IC (integrated circuit) manufacturing, a group of technologies for sub-lOOnm process modeling and DFM (design for manufacturability) problem location was introduced. And several Resolution Enhancement Technologies (RET) were adopted to improve the production yield and manufacturability of ICs. Based on them, the specific consideration in nanometer-scale standard cell design including the new design rules and design styles was proposed and some typical patterns with DFM problems were discussed in detail. As examples of verification, a set of DFM-friendly 90nm standard cell are designed and tested.
Keywords :
Application specific integrated circuits; Design for manufacture; Design methodology; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit technology; Lithography; Manufacturing processes; Production; Virtual manufacturing;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
DOI :
10.1109/EDSSC.2005.1635407
