High-order continuous-time incremental ΣΔ ADC for multi-channel applications

A novel high-order single-loop incremental sigma- delta ADC for multi-channel applications is proposed. High- order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage regarding the integrators´ gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts. This advantage leads to possible low power solutions for multi-channel applications.