High-order continuous-time incremental ΣΔ ADC for multi-channel applications

Author

Garcia, Julian ; Rusu, Ana

Author_Institution

Sch. of Inf. & Commun. Technol. (ICT), R. Inst. of Technol. (KTH), Kista, Sweden

fYear

2011

fDate

15-18 May 2011

Firstpage

1121

Lastpage

1124

Abstract

A novel high-order single-loop incremental sigma- delta ADC for multi-channel applications is proposed. High- order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage regarding the integrators´ gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts. This advantage leads to possible low power solutions for multi-channel applications.

Keywords

analogue-digital conversion; higher order statistics; 3rd order single-bit modulator; analogue-to-digital converters; gain-bandwidth requirement; high-order continuous-time incremental ΣΔ ADC; high-order single-loop incremental sigma-delta ADC; multichannel applications; Electroencephalography; Jitter; Modulation; Noise; Quantization; Thyristors; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5937767

Filename

5937767