Title :
A RNS Montgomery multiplication architecture
Author :
Schinianakis, Dimitris ; Stouraitis, Thanos
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Patras, Rion, Greece
Abstract :
A novel algorithm and VLSI architecture for Residue Number System (RNS) Montgomery modular multiplication are presented in this paper. An analysis of binary-to- RNS and RNS-to-binary conversions along with the proposed RNS Montgomery multiplication reveals common datapaths and a unified add/multiply architecture is derived that supports all aforementioned operations in the same hardware. The proposed algorithm is fully executed in RNS and the cost of the input/output conversions is compensated by the speed up of operations due to the inherent parallelism of RNS. If used repeatedly, the proposed architecture supports modular exponentiation and modular inversion as well, thus forming an end-to-end alternative for cryptographic implementations.
Keywords :
VLSI; cryptography; integrated circuit design; residue number systems; Montgomery multiplication architecture; RNS-to-binary conversions; VLSI architecture; binary-to-RNS conversions; cryptographic implementations; input-output conversions; modular exponentiation; modular inversion; residue number system; unified add-multiply architecture; Computer architecture; Computers; Elliptic curve cryptography; Elliptic curves; Hardware; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937776
