Title :
Pin assignment for multi-FPGA systems
Author :
Hauck, Scott ; Borriello, Gaetano
Author_Institution :
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
Abstract :
There is currently great interest in using systems of FPGAs for logic emulators, custom computing devices, and software accelerators. An important step in making these technologies more generally useful is to develop completely automatic mapping tools from high-level specifications to FPGA programming files. We examine one step in this automatic mapping process, the selection of FPGA pins to use for routing inter-FPGA signals. We present an algorithm that greatly increases mapping speed while also improving mapping quality
Keywords :
circuit layout CAD; logic CAD; logic arrays; FPGA programming files; automatic mapping tools; custom computing devices; high-level specifications; logic emulators; mapping speed; multi-FPGA systems; pin assignment; software accelerators; Circuit synthesis; Computer science; Field programmable gate arrays; Logic devices; Logic programming; Partitioning algorithms; Pins; Routing; Signal mapping; Wires;
Conference_Titel :
FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-5490-2
DOI :
10.1109/FPGA.1994.315593
