Hardware-software codesign of multidimensional programs

Author

Luk, Wayne ; Wu, Teddy ; Page, Ian

Author_Institution

Comput. Lab., Oxford Univ., UK

fYear

1994

fDate

10-13 Apr 1994

Firstpage

82

Lastpage

90

Abstract

Presents a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-and-conquer structure, with the “divide” and “merge” phases carried out by a general-purpose processor, while the “conquer” phase is handled by application-specific hardware. The partitioning strategy has been captured in a simple functional language, and we have automated the production of partitioned programs in this language. Our approach has been tested on an FPGA-based system using a number of computer vision algorithms, including the Canny edge detector, and the performance is compared against executing the programs on the PC host

Keywords

computer vision; edge detection; firmware; functional programming; logic arrays; merging; microcomputer applications; parallel programming; Canny edge detector; FPGA-based system; PC host; application-specific hardware; automatic partitioned program production; computer vision algorithms; divide-and-conquer structure; execution acceleration; functional language; general-purpose processor; hardware coprocessor; hardware-software codesign; merge phase; multidimensional programs; parametrised program partitioning; performance; Acceleration; Computer vision; Coprocessors; Field programmable gate arrays; Hardware; Laboratories; Multidimensional systems; Partitioning algorithms; Programmable logic arrays; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-5490-2

Type

conf

DOI

10.1109/FPGA.1994.315604

Filename

315604