A hierarchical 3-D floorplanning algorithm for many-core CMP networks

With technology scaling and 3D integration, it is becoming possible to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP). Manual floorplanning of chips becomes more time consuming and inefficient as complexity increases. Compared to traditional ASIC architectures, CMPs have homogenous processing elements and regular network topologies. In this paper, we propose a floorplan technique that can exploit the regularity and structure present in 3D-CMP networks. We can generate floorplans for different topologies under different design constraints. Compared with traditional floorplanning approaches, our tool shows significant advantages in reducing the total interconnect wire-length and power.