Distributed LC resonant clock tree synthesis

Clock networks in high-performance designs are extremely power hungry. One potential method for reducing the power consumption is to use distributed LC tanks in which energy is conserved by shifting it between electrical and magnetic forms at the resonant frequency. However, no physical algorithms to physically synthesize resonant trees have been proposed. In order to utilize such techniques in ASICs, this work presents the first algorithm to synthesize resonant regional clock trees. Our results suggest that, on average, we can reduce clock power consumption by 41.7% at 2Ghz with no degredation to skew compared to a minimum buffer insertion algorithm.