Compiling to the gate level for a reconfigurable co-processor

Author

Wo, David ; Forward, Kevin

Author_Institution

Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia

fYear

1994

fDate

10-13 Apr 1994

Firstpage

147

Lastpage

154

Abstract

This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the code make the most intense use of the processor. These parts are then compiled to the gate level and implemented in the coprocessor. Speedups in program execution time of about 20 are obtained by this method by comparison with an IPC Sparcstation

Keywords

logic arrays; program compilers; reconfigurable architectures; C code; C-compiler; FPGA; IPC Sparcstation; gate level; program execution time; programmable coprocessor; reconfigurable co-processor; Clocks; Computer aided instruction; Computer architecture; Coprocessors; Field programmable gate arrays; Frequency; Hardware; Parallel processing; Reduced instruction set computing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-5490-2

Type

conf

DOI

10.1109/FPGA.1994.315607

Filename

315607