Title :
Finding lines and building pyramids with SPLASH 2
Author :
Abbott, A. Lynn ; Athanas, Peter M. ; Chen, Luna ; Elliott, Robert L.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
This paper describes the design and implementation of two image-processing algorithms using the SPLASH 2 custom computing platform. SPLASH 2 is a reconfigurable system that can be tailored to perform a wide variety of tasks. The particular tasks discussed here are the Hough transform. A well-known technique for detecting lines in an image, and pyramid generation. The process of transforming a single image into a set of filtered images with successively lower spatial resolution. This paper describes how these computationally intensive processes have been mapped onto SPLASH 2 hardware. Both processes have been designed to operate at high speed. In particular, the generation of both Gaussian (low-pass) and Laplacian (band-pass) pyramids can occur concurrently in real time using images from a video camera, assuming the standard frame rate of 30 images per second. Results are presented to illustrate the efficacy of reconfigurable FPGA-based machines to image processing applications
Keywords :
Hough transforms; edge detection; image processing; real-time systems; reconfigurable architectures; special purpose computers; Gaussian pyramids; Hough transform; Laplacian pyramids; SPLASH 2; custom computing platform; filtered images; image analysis; image processing applications; image-processing algorithms; line detection; pyramid generation; real time; reconfigurable FPGA-based machines; reconfigurable system; spatial resolution; standard frame rate; video camera; Algorithm design and analysis; Band pass filters; Buildings; Cameras; Hardware; Image generation; Image processing; Laplace equations; Process design; Spatial resolution;
Conference_Titel :
FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-5490-2
DOI :
10.1109/FPGA.1994.315608