A 10-bit pipelined ADC for high speed, low power applications

A pipelined ADC is presented in which the key component, the comparator, is designed using a latch structure which decreases the settling time and minimizes static power dissipation. Offset errors caused by device mismatch are cancelled using an autozeroing technique. The gain cell and subtractor is designed using a differential mode source follower to maximize the speed and minimize the power consumption and die area. The automatic gain calibration scheme is addressed. The circuit implementation enables operation at a 20 MHz sampling rate with only 25 mW average power dissipation. It achieves 10-bit resolution with the die area being less than 0.8 mm/sup 2/ in a 0.8 /spl mu/m technology.