DocumentCode
1991288
Title
Efficient algorithmic circuit verification using indexed BDDs
Author
Bitner, J. ; Jain, J. ; Abadir, M. ; Abraham, J.A. ; Fussell, D.S.
Author_Institution
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear
1994
fDate
15-17 June 1994
Firstpage
266
Lastpage
275
Abstract
The Indexed Binary Decision Diagram (IBDD), a Boolean function representation scheme, provides a compact representation for functions whose OBDD representation is intractably large. In this paper, we present more efficient algorithms for satisfiability testing and equivalence checking of IBDDs. Efficient verification of Booth multipliers, as well as practical strategies for polynomial time verification of some classes of unsigned array multipliers, are demonstrated experimentally. Our results show that the verification of many instances of functions whose analysis is intractable using OBDDs, such as multipliers and the hidden-weighted-bit function, can be done efficiently using IBDDs.<>
Keywords
Boolean functions; combinatorial circuits; formal verification; logic testing; multiplying circuits; Boolean function representation; Indexed Binary Decision Diagram; OBDD representation; algorithmic circuit verification; equivalence checking; hidden-weighted-bit function; indexed BDDs; multipliers; polynomial time verification; satisfiability testing; unsigned array multipliers; Boolean functions; Circuit analysis; Data structures; Input variables; Jacobian matrices; Laboratories; Microelectronics; Polynomials; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on
Conference_Location
Austin, TX, USA
Print_ISBN
0-8186-5520-8
Type
conf
DOI
10.1109/FTCS.1994.315633
Filename
315633
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