Title :
Sliding Window Method for stochastic LDPC decoder
Author :
Chen, Jienan ; Hu, Jianhao
Author_Institution :
Sci. & Technol. on Commun., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper proposes a Sliding Window Method (SWM) for stochastic Low Density Parity Check (LDPC) decoder designing. The SWM is formulated for solving the latch-up problem in the Variable Nodes (VN) information updating. The bit in the latch-up state is evolved from the information bit in the sliding window. Then, an optimized hardware structure is proposed for SWM. Compared with traditional VN structure, the SWM require about 35% less hardware resources to achieve the same BER performance.
Keywords :
error statistics; parity check codes; stochastic processes; BER performance; SWM; VN structure; latch-up problem; latch-up state; optimized hardware structure; sliding window method; stochastic LDPC decoder; stochastic low density parity check decoder designing; variable node information; Bit error rate; Decoding; Hardware; Iterative decoding; Logic gates; Radiation detectors; Bit-Error Ratio (BER); Low Density Parity Check (LDPC); Sliding Window Method (SWM); Stochastic decoding;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937811
