Title :
A high-speed parallel sensing scheme for multi-level non-volatile memories
Author :
Calligaro, Cristiano ; Gastaldi, Roberto ; Manstretta, Alessandro ; Torelli, Guido
Author_Institution :
Dipt. di Elettronica, Pavia Univ., Italy
Abstract :
A parallel sensing scheme for multi-level non-volatile memories (ML NVM) is presented. A single comparison step is used to achieve high sensing speed. To this purpose, a high-speed low-voltage current comparator is used. Experimental evaluations on a 0.6-μm EPROM test chip demonstrated the feasibility of 4-level-cell NV MLMs from the sensing standpoint. A read throughput of 12 MB/s is achieved with the proposed 4-level-cell memory architecture. Multi-level storage is achieved by using a program-verified scheme to obtain tight cell threshold voltage distribution. Overall sensing area overhead for a 32-Mbit chip is in the range of 1%
Keywords :
EPROM; cellular arrays; comparators (circuits); integrated circuit testing; memory architecture; 0.6 micron; 12 MB/s; 32 Mbit; EPROM test chip; cell threshold voltage distribution; four-level-cell memory architecture; high-speed parallel sensing scheme; low-voltage current comparator; multi-level nonvolatile memories; program-verified scheme; read throughput; sensing area overhead; sensing speed; Channel hot electron injection; EPROM; Energy consumption; Flash memory; Memory architecture; Nonvolatile memory; Testing; Threshold voltage; Throughput; Tunneling;
Conference_Titel :
Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8099-7
DOI :
10.1109/MTDT.1997.619401
