DocumentCode
1991705
Title
Diagnosis of processor arrays
Author
Baldelli, L. ; Maestrini, P.
Author_Institution
Dipartimento di Inf., Pisa Univ., Italy
fYear
1994
fDate
15-17 June 1994
Firstpage
48
Lastpage
54
Abstract
This paper introduces an approach to diagnosis of processor arrays, assuming that processors are horizontally, vertically and diagonally connected to their neighbors. The proposed algorithm subdivides the array into clusters containing nine processors and requires three steps. In the first step each cluster executes tests according to a rosace pattern, and clusters for which all test results were zero are classified as Z-Cs. The remaining cluster, which contain at least one fault, are classified NZ-Cs. In the second step. Z-Cs are combined into aggregates (ZACS) and one Z-ACs is identified as a fault-free core of the array. The third step leads to identification of the state (of faulty or non faulty) of more nodes. The diagnosis is proved to be correct, although possibly incomplete, assuming that the number of faults is less that a bound T, which is an increasing function of the size of the array.<>
Keywords
computer testing; logic arrays; logic testing; multiprocessing systems; sequential circuits; VLSI; fault-free core; multiprocessor systems; processor arrays; rosace pattern; system diagnosis; Aggregates; Clustering algorithms; Communication standards; Fault diagnosis; Hypercubes; Interconnected systems; Multiprocessing systems; Performance evaluation; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on
Conference_Location
Austin, TX, USA
Print_ISBN
0-8186-5520-8
Type
conf
DOI
10.1109/FTCS.1994.315658
Filename
315658
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