A second-order switched-capacitor ΔΣ modulator using very incomplete settling

This paper presents a novel ΔΣ circuit based on the implementation of discrete time filters using very incomplete settling. This approach allows building a ΔΣM with mostly dynamic elements thus reducing the power dissipation. A 2^nd order ΔΣM architecture, using this technique, is presented and analyzed. High-level and transient noise electrical simulations prove the validity of the concept. Electrical simulations show that the ΔΣM achieves a peak SNDR of 74.0 dB, a peak SNR of 78.6 dB and a dynamic range of 82.4 dB for a signal with a bandwidth of 300 kHz, while dissipating 204 μW from a 1.1 V power supply voltage, indicating that, a FOM of 174 dB can be reached.