Title :
A structured approach for designing low power adders
Author :
Shams, Ahmed M. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
A performance analysis of a general 1-bit full adder cell is presented. The adder cell is anatomized into smaller modules using the proposed structured approach. The modules are studied extensively and several designs of each of them are shown. Connecting combinations of designs of these modules together we construct 24 different 1-bit full adder cells (some of them are novel circuits). Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Some of the new cells outperform existing standard designs of the full adder cell.
Keywords :
CMOS integrated circuits; VLSI; adders; digital arithmetic; modules; 1 bit; 1-bit full adder cell; CMOS circuits; DSP chips; VLSI; area; low power adders; modules; performance analysis; power consumption; speed; standard designs; structured approach; Adders; Buildings; Clocks; Energy consumption; Equations; Frequency; Joining processes; Power supplies; Switching circuits; Very large scale integration;
Conference_Titel :
Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-8316-3
DOI :
10.1109/ACSSC.1997.680546
