FinFET SRAM hardening through design and technology parameters considering process variations

Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening. One is related to increasing the number of fins of the transistors composing the cross-coupled inverters. This option provides a significant increase of the cell critical charge (Q_crit), but with a cost in area. The other alternative increases the transistors fin height. Results show that a similar Q_crit gain is achieved by increasing the fin height instead of the number of fins without area overhead. The impact of process variations has been considered. Q_crit distribution has been modeled through an statistical approach based on Design of Experiments. Results are presented for a 10nm-SOI Trigate FinFET technology.