CNF encodings of cardinality in formal methods for robustness checking of gate-level circuits

With decreasing transistor sizes, the susceptibility of digital circuits to soft errors will increase. Thus, the need to efficiently evaluate the robustness of a gate-level circuit to multiple simultaneous soft errors. We compare the efficiency of various CNF schemes for encoding of cardinality constraints, which control the number of simultaneously injected soft errors in a gate-level circuit, when the robustness of the circuit is computed with SAT-based formal methods.