Design methodology for minimizing hysteretic V/sub T/-variation in partially-depleted SOI CMOS

This work demonstrates that switching-history-dependent threshold voltage variation can be minimized in partially-depleted SOI NMOS and PMOS devices by a device design which combines body-charge balance between logic states with minimum gate-body capacitive coupling and non-ideal body-source/drain diode behavior. This analysis also demonstrates that once the devices are charge-balanced supply voltage scaling naturally minimizes /spl Delta/V/sub T/.