Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage

Author

Tanaka, T. ; Momiyama, Y. ; Sugii, T.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

423

Lastpage

426

Abstract

The high frequency characteristics of DTMOS are described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 3.7 GHz for a 0.1-/spl mu/m-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.

Keywords

MOSFET; UHF field effect transistors; capacitance; microwave field effect transistors; oxidation; semiconductor device metallisation; 0.1 micron; 0.7 V; 3.7 GHz; 78 GHz; DTMOS; dynamic threshold-voltage MOSFET; gate polysilicon oxidation; high frequency characteristics; output resistance; overlapped region; parasitic capacitance; parasitic resistance; salicide technology; transconductance; ultra-low supply voltage; Cutoff frequency; Immune system; Laboratories; MOSFET circuits; Oxidation; Parasitic capacitance; Radio frequency; Threshold voltage; Transceivers; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650415

Filename

650415