• DocumentCode
    1993096
  • Title

    Design alternatives for scalable Web server accelerators

  • Author

    Song, Junehwa ; Levy-Abegnoli, E. ; Iyengar, Arun ; Dias, Daniel

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    184
  • Lastpage
    192
  • Abstract
    We study design alternatives for, and describe implementations and performance of, a scalable and highly available Web server accelerator. The accelerator runs under an embedded operating system and improves Web server performance by caching data. The basic design alternatives include a content router or a TCP router (without content routing) in front of a set of Web cache accelerator nodes, with the cache memory distributed across the accelerator nodes. Content based routing reduces cache node CPU cycles but can make the front-end router a bottleneck. With the TCP router, a request for a cached object may initially be sent to the wrong cache node; this results in larger cache node CPU cycles, but can provide a higher aggregate throughput, because the TCP router becomes a bottleneck at a higher throughput than the content router. Based on measurement of implementations, we quantify the throughput ranges in which different designs are preferable. We also examine a combination of content based and TCP routing techniques. We examine optimizations, such as different communication and data delivery methods, replication of hot objects, and cache replacement policies that take into account the fact that there might be different bottlenecks in the system at different times; depending upon which resource is likely to become a bottleneck, a different cache replacement algorithm is applied
  • Keywords
    cache storage; distributed memory systems; embedded systems; file servers; information resources; operating systems (computers); transport protocols; TCP router; TCP routing techniques; Web server performance; aggregate throughput; cache memory distribution; cache node CPU cycles; cache replacement algorithm; cache replacement policies; cached object; content based routing; content router; data caching; data delivery methods; design alternatives; embedded operating system; hot object replication; scalable Web server accelerators; throughput ranges; Acceleration; Application software; Availability; Cache memory; File systems; Kernel; Operating systems; Throughput; Uniform resource locators; Web server;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems and Software, 2000. ISPASS. 2000 IEEE International Symposium on
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-6418-X
  • Type

    conf

  • DOI
    10.1109/ISPASS.2000.842299
  • Filename
    842299