Title :
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
Author :
Wong, H.-S.P. ; Chan, K.K. ; Taur, Y.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
In this paper, we report a fabrication method that attains the "ideal" double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET\´s with a 25 nm thick silicon channel were successfully demonstrated.
Keywords :
MOSFET; silicon; vapour deposition; 25 nm; Si; channel Si thickness; fabrication method; fanned-out source/drain structure; low parasitic resistance; n-channel MOSFET; planar film deposition process; self-aligned double-gate MOSFET; Analytical models; Capacitance; Etching; Fabrication; MOSFET circuits; Monte Carlo methods; Semiconductor films; Silicon; Thickness control; Wire;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650416
