DocumentCode
1993428
Title
Design of high-speed and reusable SPI IP core based on Wishbone interface
Author
Zhou, Baowen ; Li, Dong ; Lu, Gang
Author_Institution
Sch. of Autom. & Inf. Eng., Xi´´an Univ. of Technol., Xi´´an, China
fYear
2011
fDate
16-18 Sept. 2011
Firstpage
1040
Lastpage
1042
Abstract
The SPI put forward by Motorola Company is a high-speed, full-duplex, synchronous communication bus, and its simple connect could save resources. More and more IC chips are using this protocol. Based on the wishbone bus interface, we design a high-speed and reusable SPI IP core.
Keywords
IP networks; high-speed integrated circuits; high-speed techniques; IC chips; Motorola Company; full-duplex communication bus; high-speed SPI IP core; high-speed communication bus; reusable SPI IP core; synchronous communication bus; wishbone bus interface; Automation; Companies; Educational institutions; Hardware design languages; IP networks; Presses; System-on-a-chip; IP core; SPI; Wishbone bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location
Yichang
Print_ISBN
978-1-4244-8162-0
Type
conf
DOI
10.1109/ICECENG.2011.6058000
Filename
6058000
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